| Item | Content | Total Test Case | Priority | Duration | Status |
|---|---|---|---|---|---|
| 1 | Add-in Card PHY test | 7 | 1 | 2 | |
| 1.1 | Transmitter Signal Quality Test | 1 | 1 | 1 | |
| 1.2 | Transmitter Pulse Width Jitter Test | 1 | 1 | 1 | |
| 1.3 | Transmitter Preset Test | 1 | 1 | 1 | |
| 1.4 | Transmitter Initial TX EQ Test | 1 | 1 | 1 | |
| 1.5 | Transmitter Link Equalization Response Test | 1 | 1 | 1 | |
| 1.6 | Transmitter Margining at 16GT/s Test | 1 | 1 | 1 | |
| 1.7 | Receiver Link Equalization Test | 1 | 1 | 1 | |
| 1.7 | PLL Bandwidth Test | 1 | 1 | 1 | |
| 2 | End Device Link Layer and Transaction Layer Test | 11 | 1 | 2 | |
| 2.1 | Data Link Layer Packet Rules | 1 | 1 | 1 | |
| 2.2 | LCRC and Sequence Number Rules | 1 | 1 | 1 | |
| 2.3 | LCRC and Sequence Number - TLP Receiver | 1 | 1 | 1 | |
| 2.4 | Transaction Layer Rules | 1 | 1 | 1 | |
| 2.5 | Reserved Bits in Training Sequences | 1 | 1 | 1 | |
| 2.6 | De-emphasis Request During Speed Change | 1 | 1 | 1 | |
| 2.7 | Link Equalization | 1 | 1 | 1 | |
| 2.8 | Function Level Reset | 1 | 1 | 1 | |
| 2.9 | Latency Tolerance Requests | 1 | 1 | 1 | |
| 2.10 | Link Partner Enters and Exits Compliance1 | 1 | 1 | ||
| 2.11 | L1 for D3 State | 1 | 1 | 1 | |
| 2.11 | ASPM-L1 Test | 1 | 1 | 1 |
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